Flip-flop

Abstract

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• A form of Synchronous Sequential Circuit. The output changes are regulated by a Clock Oscillator

Asynchronous inputs

Asynchronous inputs affect the state of the flip-flop independently of the clock.

• When the preset (PRE), also known as direct set (SD), is HIGH, Q is immediately set to HIGH.
• When the clear (CLR), also known as direct reset (RD), is HIGH, Q is immediately cleared to LOW.

J-K Flip-flop

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• J is basically Set, K is basically Reset. Active-high

Important

The J-K flip-flop eliminates the invalid state when both J and K are active, causing the outputs to toggle.

T Flip-flop

• When T is active, it will toggle the outputs of J-K Flip-flop