Abstract
- Stands for Memory Management Unit
- Hardware component that takes a Virtual Address and translates it into a Physical Address via the Page Table.
- This hardware-driven translation underpins virtual memory, letting each process see a consistent address space while the OS multiplexes physical memory.
Kernel is free
If there’s a TLB miss, the MMU itself (not the kernel) does a page table walk: it consults the multi-level page table in memory to resolve the mapping.
Kernel’s role
The kernel doesn’t do the page walk for each access.
On boot, the kernel sets up the initial page tables and programs the MMU with:
- How many levels to use (e.g., 4 levels on x86_64: PML4 → PDPT → PD → PT)
- How many bits are allocated to virtual page number (VPN) vs page offset.
- The base pointer to the root page table (in CR3 on x86).
After that, the hardware owns the fast path. The CPU+MMU work together to do page walks transparently.
Workflow behind TLB Miss
- CPU needs a physical address → checks the TLB
- TLB miss → MMU walks the page tables directly: uses CR3 (base) + VPN bits to index each level, fetches page table entries (PTEs) from memory & ends with a physical frame number (PFN).
- MMU fills the TLB with the new translation.
- CPU resumes execution as if nothing happened.
⚠️ The kernel only steps in if:
- The page walk hits a PTE marked “not present” → page fault exception.
- Then the kernel decides whether to allocate a page, swap it in, or kill the process.
Attention
A Page Fault occurs when the Memory Management Unit (MMU) is unable to locate a specific Memory Page in its page table.